AIODC

Active IO DaughterCard:

Implemented Custom FPGA based Daughter card for attachment to QMP Processor / Compute engine.

Hardware consisted of: two Altera Stratix_II GX FPGAs, each FPGA having two independent 256MB DDRII banks, Onboard POL Power Monitor / Control, 26.4 GB/s Aggregate IO Bandwidth, 18 Layer PCB.

Performed: System Architecture. Electrical, Mechanical, FPGA design. Microcontroller Firmware development. Prototype acquisition and Debug. 12 month duration (in conjunction with QMP).

Last Updated:

Tuesday, March 29, 2011

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