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RapidIO Serial Logical Layer IP (RLL_Core_IP Block):
• Complete implementation of RapidIO 1.2 Logical Layer Protocols in synthesizable Verilog. Utilized by customer as part of larger deliverable IP package for resale.
• This IP has been implemented in over fifty FPGA and ASIC designs
• Performed: IP Architecture. Design. Verilog Coding. Test Synthesis. Verification of all Verilog ~(50k lines)
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